View ISL6269ACRZ_8703410.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 ? fn9253.2 isl6269a high-performance notebook pwm controller the isl6269a ic is a single-phase synchronous-buck pwm controller featuring inters il's robust ripple regulator (r 3 ) technology that delivers truly superior dynamic response to input voltage and output load transients. integrated mosfet drivers and bootstrap diode result in fewer components and smaller implementation area. intersil?s r 3 technology combines the best features of fixed- frequency pwm and hysteretic pwm while eliminating many of their shortcomings. r 3 technology emplo ys an innovative modulator that synthesizes an ac ripple voltage signal v r , analogous to the output inductor ripple current. the ac signal v r enters a window comparator where the lower threshold is the error amplifier output v comp , and the upper threshold is a programmable voltage reference v w, resulting in generation of the pwm signal. the voltage reference v w sets the steady-state pwm frequency. both edges of the pwm can be modulated in response to input voltage transients and output load tr ansients, much faster than conventional fixed-frequency pwm controllers. unlike a conventional hysteretic converter, the isl6269a has an error amplifier that provides 1% voltage regulation at the fb pin. the isl6269a has a 1.5ms digital soft-start and can be started into a pre-biased output voltage. a resistor divider is used to program the output voltage setpoint. the isl6269a can be configured to operate in continuous-conduction- mode (ccm) or diode-emulation-mode (dem), which improves light-load efficiency. in ccm the controller always operates as a synchronous rectifier however, when dem is enabled the low-side mosfet is permitted to stay off, blocking negative current flow into the low-side mosfet from the output inductor. pinout isl6269a (16 ld 4x4 qfn) top view features ? high performance r 3 technology ? fast transient response ? 1% regulation accuracy: -10c to +100c and -40c to +100c ? wide input voltage range: +5.0v to +25.0v ? output voltage range: +0.6v to +3.3v ? wide output load range: 0a to 25a ? selectable diode emulation mode for increased light load efficiency ? programmable pwm frequency: 200khz to 600khz ? pre-biased output start-up capability ? integrated mosfet drivers and bootstrap diode ? internal digital soft-start ? power good monitor ? fault protection - undervoltage protection - soft crowbar overvoltage protection - low-side mosfet r ds(on) overcurrent protection - over-temperature protection - fault identification by pgood pull down resistance ? pb-free plus anneal available (rohs compliant) applications ? pci express graphical processing unit ? auxiliary power rail ?vrm ? network adapter 1 3 4 15 16 14 13 2 12 10 9 11 6 578 gnd boot pgood ug phase vo comp fset fb isen pvcc pgnd lg en vin fccm vcc ordering information part number (note) part marking temp range (c) package (pb-free) pkg. dwg. # ISL6269ACRZ* 62 69acrz -10 to +100 16 ld 4x4 qfn l16.4x4 isl6269airz* 62 69airz -40 to +100 16 ld 4x4 qfn l16.4x4 *add ?-t? suffix for tape and reel. note: intersil pb-free plus anneal pr oducts employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. data sheet may 30, 2007 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2005, 2006, 2007. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 fn9253.2 may 30, 2007 isl6269a block diagram figure 1. schematic block diagram v w v r pwm r pgood en fb comp isen boot ug lg pvcc pgnd fccm phase uvp s q por digital soft-start 150ot shoot through protection driver driver v comp pwm control vin fset vcc vo v ref + ? ovp + ? ea ? + ea ocp + ? ? + g m v in ? + g m v o ? + ? + ? + c r pwm frequency control gnd package bottom i oc 30 90 60 ? +
3 fn9253.2 may 30, 2007 typical application vcc pvcc fset gnd en fccm pgood comp fb vin phase isen boot ug lg pgnd c pvcc c out l out isl6269a vo c vcc r vcc r pgood q high_side r sen r fset c fset r top r bottom r comp c comp1 c comp2 c boot v in c in v out 0.6v to 3.3v q low_side 5v to 25v 5v figure 2. isl6269a typical application schematic isl6269a
4 fn9253.2 may 30, 2007 absolute voltage ratings isen, vin to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +28v vcc, pgood to gnd . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +7.0v pvcc to pgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +7.0v gnd to pgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +0.3v en, fccm . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to gnd, vcc +3.3v vo, fb, comp, fset . . . . . . . . . . . . . . . -0.3v to gnd, vcc +0.3v phase to gnd (dc) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +28v (<100ns pulse width, 10 j) . . . . . . . . . . . . . . . . . . . . . . . . . -5.0v boot to gnd, or pgnd . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +33v boot to phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +7v ug (dc) . . . . . . . . . . . . . . . . . . . . . . .-0.3v to phase, boot +0.3v (<200ns pulse width, 20 j) . . . . . . . . . . . . . . . . . . . . . . . . -4.0v lg (dc) . . . . . . . . . . . . . . . . . . . . . . . .-0.3v to pgnd, pvcc +0.3v (<100ns pulse width, 4 j) . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0v thermal information thermal resistance (typical, notes 1, 2) ja (c/w) jc (c/w) qfn package. . . . . . . . . . . . . . . . . . . . 48 11.5 junction temperature range. . . . . . . . . . . . . . . . . .-55 c to +150 c operating temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISL6269ACRZ . . . . . . . . . . . . . . . . . . . . . . . . . . .-10c to +100c isl6269airz . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +100c storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65 c to +150 c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp recommended operating conditions ambient temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISL6269ACRZ . . . . . . . . . . . . . . . . . . . . . . . . . . .-10c to +100c isl6269airz . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +100c supply voltage (vin to gnd) . . . . . . . . . . . . . . . . . . . . . . 5v to 25v vcc to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5v 5% pvcc to pgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5v 5% caution: stress above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress onl y rating and operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. notes: 1. ja is measured in free air with the component mounted on a high ef fective thermal conductivity te st board with ?direct attach? fe atures. see tech brief tb379. 2. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications these specifications apply for v in = 15v, t a = -40c to +100c, unless otherwise stated. all typical specifications t a = +25c, vcc = 5v, pvcc = 5v, vin = 15v parameter symbol test conditions min typ max unit vin vin input bias current i vin en = 5v, vin = 5v - 6.5 10 a en = 5v, vin = 25v - 26 35 a vin shutdown current i vin_shdn en = gnd, vin = 25v - 0.1 1.0 a vcc and pvcc vcc input bias current i vcc en = 5v, fccm = gnd, fb = 0.65v - 1.7 2.5 ma vcc shutdown current i vcc_shdn en = gnd, vcc = 5v - 0.1 1.0 a pvcc shutdown current i pvcc_shdn en = gnd, pvcc = 5v - 0.1 1.0 a vcc por threshold rising vcc por threshold voltage v vcc_thr t a = -10c to +100c 4.35 4.45 4.55 v 4.33 4.45 4.55 v falling vcc por threshold voltage v vcc_thf t a = -10c to +100c 4.10 4.20 4.30 v 4.08 4.20 4.30 v regulation reference voltage v ref - 0.6 - v regulation accuracy fb connected to comp -1 - +1 % pwm frequency range f sw fccm = 5v 200 - 600 khz frequency-set accuracy f sw = 300khz -12 - +12 % vo range v vo 0.60 - 3.30 v vo input leakage i vo vo = 0.60v - 1.3 - a vo = 3.30v - 7.0 - a error amplifier fb input bias current i fb fb = 0.60v -0.5 - +0.5 a isl6269a
5 fn9253.2 may 30, 2007 comp source current i comp_src fb = 0.40v, comp = 3.20v - 2.5 - ma comp sink current i comp_snk fb = 0.80v, comp = 0.30v - 0.3 - ma comp high clamp voltage v comp_hc fb = 0.40v, sink 50 a 3.10 3.40 3.65 v comp low clamp voltage v comp_lc fb = 0.80v, source 50 a 0.09 0.15 0.21 v power good pgood pull-down impedance r pg_ss pgood = 5ma sink, t a = -10c to +100c 75 95 125 pgood = 5ma sink 67 95 125 r pg_uv pgood = 5ma sink, t a = -10c to +100c 75 95 125 pgood = 5ma sink 67 95 125 r pg_ov pgood = 5ma sink, t a = -10c to +100c 50 63 85 pgood = 5ma sink 45 63 85 r pg_oc pgood = 5ma sink, t a = -10c to +100c 25 32 45 pgood = 5ma sink 22 32 45 pgood leakage current i pgood pgood = 5v - 0.1 1.0 a pgood maximum sink current (note 3) - 5.0 - ma pgood soft-start delay t ss en high to pgood high, t a = -10c to +100c 2.20 2.75 3.30 ms en high to pgood high 2.20 2.75 3.50 ms gate driver ug pull-up resistance r ugpu 200ma source current - 1.0 1.5 ug source current (note 3) i ugsrc ug - phase = 2.5v - 2.0 - a ug sink resistance r ugpd 250ma sink current - 1.0 1.5 ug sink current (note 3) i ugsnk ug - phase = 2.5v - 2.0 - a lg pull-up resistance r lgpu 250ma source current - 1.0 1.5 lg source current (note 3) i lgsrc lg - pgnd = 2.5v - 2.0 - a lg sink resistance r lgpd 250ma sink current - 0.5 0.9 lg sink current (note 3) i lgsnk lg - pgnd = 2.5v - 4.0 - a ug to lg deadtime t ugflgr ug falling to lg rising, no load - 21 - ns lg to ug deadtime t lgfugr lg falling to ug rising, no load - 14 - ns bootstrap diode forward voltage v f pvcc = 5v, i f = 2ma - 0.58 - v reverse leakage i r v r = 25v - 0.2 - a control inputs en high threshold v enthr 2.0 -- v en low threshold v enthf -- 1.0 v fccm high threshold v fccmthr 2.0 -- v fccm low threshold v fccmthf -- 1.0 v en leakage i enl en = 0v - 0.1 1.0 a i enh en = 5.0v - 0.1 1.0 a fccm leakage i fccml fccm = 0v - 0.1 1.0 a i fccmh fccm = 5.0v - 2.0 - a electrical specifications these specifications apply for v in = 15v, t a = -40c to +100c, unless otherwise stated. all typical specifications t a = +25c, vcc = 5v, pvcc = 5v, vin = 15v (continued) parameter symbol test conditions min typ max unit isl6269a
6 fn9253.2 may 30, 2007 functional pin descriptions gnd (bottom pad) signal common of the ic. unless otherwise stated, signals are referenced to the g nd pin, not the pgnd pin. vin (pin 1) the vin pin measures the conver ter input voltage which is a required input to the r 3 pwm modulator. connect across the drain of the high-side mosfet to the gnd pin. vcc (pin 2) the vcc pin is the input bias voltage for the ic. connect +5v from the vcc pin to the g nd pin. decouple with at least 1f of a mlcc capacitor from the vcc pin to the gnd pin. fccm (pin 3) the fccm pin configures the cont roller to operate in forced- continuous-conduction-mode (fccm) or diode-emulation- mode (dem.) dem is disabled when the fccm pin is pulled above the rising threshold voltage v fccmthr , conversely dem is enabled when the fccm pin is pulled below the falling threshold voltage v fccmthf. en (pin 4) the en pin is the on/off switch of the ic. the soft-start sequence begins when the en pin is pulled above the rising threshold voltage v enthr and vcc is above the power-on reset (por) rising threshold voltage v vcc_thr . when the en pin is pulled below the falling threshold voltage v enthf pwm immediately stops. comp (pin 5) the comp pin is the output of the control-loop error amplifier. compensation components for the control-loop connect across the comp and fb pins. fb (pin 6) the fb pin is the inverting input of the control-loop error amplifier. the converter output voltage regulates to 600mv from the fb pin to the gnd pi n. program the desired output voltage with a resistor network connected across the vo, fb, and gnd pins. select the resi stor values such that fb to gnd is 600mv when the converter output voltage is at the programmed regulation value. fset (pin 7) the fset pin programs the pwm switching frequency. program the desired pwm frequency with a resistor and a capacitor connected across the fset and gnd pins. vo (pin 8) the vo pin measures the converter output voltage and is used exclusively as an input to the r 3 pwm modulator. connect at the physical location where the best output voltage regulation is desired. isen (pin 9) the isen pin programs the threshold of the ocp overcurrent fault protection . program the desired ocp threshold with a resistor connected across the isen and phase pins. the ocp threshold is programmed to detect the peak current of the output inductor. the peak current is the sum of the dc and ac components of the inductor current. pgnd (pin 10) the pgnd pin conducts the turn-off transient current through the lg gate driver. the pgnd pin must be connected to complete the pulldown circuit of the lg gate driver. the pgnd pin should be connected to the source of the low-side mosfet through a low impedance path, preferably in parallel with the trace connecting the lg pin to the gate of the low-side mosfet. the adaptive shoot- through protection circuit, measures the low-side mosfet gate-source voltage from t he lg pin to the pgnd pin. protection isen ocp threshold i oc isen sourcing, t a = -10c to +100c 19 26 33 a isen sourcing 17 26 33 a isen short-circuit threshold i sc isen sourcing - 50 - a uvp threshold v uv 81 84 87 % ovp rising threshold v ovr 113 116 119 % ovp falling threshold v ovf 100 103 106 % otp rising threshold (note 3) t otr - 150 - c otp hysteresis (note 3) t othys - 25 - c note: 3. guaranteed by characterization. electrical specifications these specifications apply for v in = 15v, t a = -40c to +100c, unless otherwise stated. all typical specifications t a = +25c, vcc = 5v, pvcc = 5v, vin = 15v (continued) parameter symbol test conditions min typ max unit isl6269a
7 fn9253.2 may 30, 2007 lg (pin 11) the lg pin is the output of the low-side mosfet gate driver. connect to the gate of the low-side mosfet. pvcc (pin 12) the pvcc pin is the input voltage bias for the lg low-side mosfet gate driver. connect +5 v from the pvcc pin to the pgnd pin. decouple with at least 1f of an mlcc capacitor across the pvcc and pgnd pins. boot (pin 13) the boot pin stores the input voltage for the ug high-side mosfet gate driver. connect an mlcc capacitor across the boot and phase pins. the boot capacitor is charged through an internal boot diode connected from the pvcc pin to the boot pin, each ti me the phase pin drops below pvcc minus the voltage dropped across the internal boot diode. ug (pin 14) the ug pin is the output of the high-side mosfet gate driver. connect to the gate of the high-side mosfet. phase (pin 15) the phase pin detects the vo ltage polarity of the phase node and is also the current return path for the ug high-side mosfet gate driver. connect the phase pin to the node consisting of the high-side mosfet source, the low-side mosfet drain, and the output inductor. pgood (pin 16) the pgood pin is an open-drain output that indicates when the converter is able to supply regulated voltage. connect the pgood pin to +5v through a pull-up resistor. theory of operation modulator the isl6269a is a hybrid of fixed frequency pwm control, and variable frequency hysteretic control. intersil?s r 3 technology can simultaneously affect the pwm switching frequency and pwm duty cycle in response to input voltage and output load transients. th e term ?ripple? in the name ?robust-ripple-regulator? refers to the converter output inductor ripple current, not the converter output ripple voltage. the r 3 modulator synthesizes an ac signal v r , which is an ideal representation of the output inductor ripple current. the duty-cycle of v r is the result of charge and discharge current through a ripple capacitor c r . the current through c r is provided by a transconductance amplifier g m that measures the vin and vo pin voltages. the positive slope of v r can be written as: the negative slope of v r can be written as: where g m is the gain of the transconductance amplifier. a window voltage v w is referenced with respect to the error amplifier output voltage v comp , creating an envelope into which the ripple voltage v r is compared. the amplitude of v w is set by a resistor connected across the fset and gnd pins. the v r, v comp, and v w signals feed into a window comparator in which v comp is the lower threshold voltage and v w is the higher threshold voltage. figure 3 shows pwm pulses being generated as v r traverses the v w and v comp thresholds . the pwm switching frequency is proportional to the slew rates of the positive and negative slopes of v r; the pwm switching frequency is inversely proportional to the voltage between v w and v comp. power-on reset the isl6269a is disabled until the voltage v vcc has increased above the rising power-on reset (por) v vcc_thr threshold voltage. the controller will become once again disabled when the voltage v vcc decreases below the falling por v vcc_thf threshold voltage. en, soft-start, and pgood the isl6269a uses a digital soft-start circuit to ramp the output voltage of the converter to the programmed regulation setpoint at a predictable slew rate. the slew rate of the soft-start sequence has been selected to limit the inrush current through the output capacitors as they charge to the desired regulation voltage. when the en pin is pulled above the rising en threshold voltage v enthr the pgood soft-start delay t ss starts and the output voltage begins to rise. the output voltage enter s regulation in approximately 1.5ms and the pgood pin goes to high impedance once t ss has elapsed. v rpos g m () v in v out ? () ? = (eq. 1) v rneg g m v out ? = (eq. 2) ripple capacitor voltage c r error amplifier voltage v comp window voltage v w pwm figure 3. modulator waveforms during load transient isl6269a
8 fn9253.2 may 30, 2007 the pgood pin indicates when the converter is capable of supplying regulated voltage. the pgood pin is an undefined impedance if v vcc has not reached the rising por threshold v vcc_thr , or if v vcc is below the falling por threshold v vcc_thf . the isl6269a features a unique fault- identification capability that can drastically reduce trouble- shooting time and effort. the pull-down resistance of the pgood pin corresponds to the fault status of the controller. during soft-start or if an undervoltage fault occurs, the pgood pulldown resistance is 95 , or 30 for an overcurrent fault, or 60 for an overvoltage fault. mosfet gate-drive outputs lg and ug the isl6269a has internal gate-drivers for the high-side and low-side n-channel mosfets. the lg gate-driver is optimized for low duty-cycle app lications where the low-side mosfet conduction losses are dominant, requiring a low r ds(on) mosfet. the lg pulldown resistance is small in order to clamp the gate of the mosfet below the v gs(th) at turnoff. the current transient through the gate at turnoff can be considerable because the switching charge of a low r ds(on) mosfet can be large. adaptive shoot-through protection prevents a gate-driv er output from turning on until the opposite gate-driver output has fallen below approximately 1v. the dead-time shown in figure 5. is extended by the additional peri od that the falling gate voltage stays above the 1v threshold. the high-side gate-driver output voltage is measured ac ross the ug and phase pins while the low-side gate-driver output voltage is measured across the lg and pgnd pins. the power for the lg gate-driver is sourced directly from the pvcc pin. the power for the ug gate-driver is s ourced from a ?boot? capacitor connected across the boot and phase pins. the boot capacitor is charged from a 5v bias supply through a ?boot diode? each time the low-side mosfet turns on, pulling the phase pin low. the isl6269a has an integrated boot diode connected from the pvcc pin to the boot pin. diode emulation the isl6269a normally operates in continuous-conduction- mode (ccm), minimizing conduction losses by forcing the low-side mosfet to operate as a synchronous rectifier. an improvement in light-load efficiency is achieved by allowing the converter to operate in diode-emulation-mode (dem), where the low-side mosfet behaves as a smart-diode, forcing the device to block negative inductor current flow. the isl6269a can be configured to operate in dem by setting the fccm pin low. setting the fccm pin high will disable dem. positive-going inductor current flows from either the source of the high-side mosfet, or the drain of the low-side mosfet. negative-going inductor current usually flows into the drain of the low-side mosfet. when the low-side mosfet conducts positive inductor current, the phase voltage will be negative with respect to the gnd and pgnd pins. conversely, when the low-side mosfet conducts negative inductor current, the phase voltage will be positive with respect to the gnd and pgnd pins. negative inductor current occurs when the output load current is less than ? the inductor ripple current. sinking negative inductor current through the low-side mosfet lowers efficiency through unnecessary conduction losses. efficiency can be further improved with a reduction of unnecessary switching losses by reducing the pwm frequency. it is characteristic of the r 3 architecture for the pwm frequency to decrease while in diode emulation. the extent of the frequency reduction is proportional to the reduction of load current. upon entering dem, the pwm frequency makes an initial step-reduction because of a 33% step-increase of the window voltage v w . with fccm pulled low, the converter will automatically enter dem after the phase pin has detected positive voltage, table 1. pgood pull-down resistance condition pgood resistance vcc below por undefined soft start or undervoltage 95 overvoltage 60 overcurrent 30 en vcc and pvcc vout pgood 1.5ms 2.75ms figure 4. soft-start sequence figure 5. lg and ug dead-time ug lg 50% 50% t lgfugr t ugflgr isl6269a
9 fn9253.2 may 30, 2007 while the lg gate-driver pin is high, for eight consecutive pwm pulses. the converter will return to ccm on the following cycle after the phase pin detects negative voltage, indicating that the body diode of the low-side mosfet is conducting positive inductor current. overcurrent and short-circuit protection the overcurrent protection (ocp) and short circuit protection (scp) setpoint is programmed with resistor r sen that is connected across the isen and phase pins. the phase pin is connected to the drain terminal of the low-side mosfet. the scp setpoint is internally set to twice the ocp setpoint. when an ocp or scp fault is detected, the pgood pin will pulldown to 30 and latch off the converter. the fault will remain latched until the en pin has been pulled below the falling en threshold voltage v enthf or if v vcc has decayed below the falling por threshold voltage v vcc_thf . the ocp circuit does not directly detect the dc load current leaving the converter. the ocp circuit detects the peak of positive-flowing output inductor current. the low-side mosfet drain current i d is assumed to be equal to the positive output inductor current when the high-side mosfet is off. the inductor current develops a negative voltage across the r ds(on) of the low-side mosfet that is measured shortly after the lg gate-driver output goes high. the isen pin sources t he ocp sense current i sen, through the ocp programming resistor r sen, forcing the isen pin to zero volts with respect to the gnd pin. the negative voltage across the phase and gnd pins is nulled by the voltage dropped across r sen as i sen conducts through it. an ocp fault occurs if i sen rises above the ocp threshold current i oc while attempting to null the negative voltage across the phase and gnd pins. i sen must exceed i oc on all the pwm pulses that occur within 20s. if i sen falls below i oc on a pwm pulse before 20s has elapsed, the timer will be reset. an scp fault will occur within 10s when i sen exceeds twice i oc. the relationship between i d and i sen is written as: the value of r sen is then written as: where: -r sen ( ) is the resistor used to program the overcurrent setpoint -i sen is the current sense current that is sourced from the isen pin -i oc is the i sen threshold current sourced from the isen pin that will activate the ocp circuit -i fl is the maximum continuous dc load current -i pp is the inductor peak-to-peak ripple current -oc sp is the desired overcurrent setpoint expressed as a multiplier relative to i fl overvoltage protection when an ovp fault is detect ed, the pgood pin will pull down to 60 and latch-off the converter. the ovp fault will remain latched until v vcc has decayed below the falling por threshold voltage v vcc_thf . the ovp fault detection circuit triggers after the voltage across the fb and gnd pins has increased above the rising overvoltage threshold v ovr. although the converter has latched-off in response to an ov p fault, the lg gate-driver output will retain the ability to toggle the low-side mosfet on and off, in response to the output voltage transversing the v ovr and v ovf thresholds. undervoltage protection when a uvp fault is detected, the pgood pin will pull down to 95 and latch-off the converter. the fault will remain latched until the en pin has been pulled below the falling en threshold voltage v enthf or if v vcc has decayed below the falling por threshold voltage v vcc_thf . the uvp fault detection circuit triggers after the voltage across the fb and gnd pins has fallen below the undervoltage threshold v uv . over-temperature when the temperature of the isl6269a increases above the rising threshold temperature t otr , the ic will enter an otp state that suspends the pwm , forcing the lg and ug gate-driver outputs low. the status of the pgood pin does not change nor does the converter latch-off. the pwm remains suspended until the ic temperature falls below the hysteresis temperature t othys at which time normal pwm operation resumes. the otp state can be reset if the en pin is pulled below the falling en threshold voltage v enthf or if v vcc decays below the falling por threshold voltage v vcc_thf . all other protection circuits function normally during otp. it is likely that the ic will detect an uvp fault because in the absence of pwm, the output voltage immediately decays below the undervoltage threshold v uv ; the pgood pin will pulldown to 95 and latch-off the converter. the uvp fault will remain latched until the en pin has been pulled below the falling en threshold voltage v enthf or if v vcc has decayed below the falling por threshold voltage v vcc_thf . i sen r sen ? i d r ds on () ? = (eq. 3) (eq. 4) r sen i fl i pp 2 -------- - + ?? ?? oc sp ? r ds on () ? i oc ---------------------------------------------------------------------------- = isl6269a
10 fn9253.2 may 30, 2007 programming the output voltage when the converter is in regulation there will be 600mv from the fb pin to the gnd pin. connect a two-resistor voltage divider across the vo pin and the gnd pin with the output node connected to the fb pin. scale the voltage-divider network such that the fb pi n is 600mv with respect to the gnd pin when the converter is regulating at the desired output voltage. the output vo ltage can be programmed from 600mv to 3.3v. programming the output voltage is written as: where: -v out is the desired output voltage of the converter -v ref is the voltage that the converter regulates to between the fb pin and the gnd pin -r top is the voltage-programming resistor that connects from the fb pin to the vo pin. in addition to setting the output voltage, this resistor is part of the loop compensation network -r bottom is the voltage-programming resistor that connects from the fb pin to the gnd pin beginning with r top between 1k to 5k , calculating r bottom is written as: programming the pwm switching frequency the isl6269a does not use a clock signal to produce pwm. the pwm switching frequency f sw is programmed by the resistor r fset that is connected from the fset pin to the gnd pin. the approximate pwm switching frequency is written as: estimating the value of r fset is written as: where: -f sw is the pwm switching frequency -r fset is the f sw programming resistor - k = 75 x 10 -12 it is recommended that whenever the control loop compensation network is modified, f sw should be checked for the correct frequency and if necessary, adjust r fset . compensation design the lc output filter has a double pole at its resonant frequency that causes the phase to abruptly roll downward. the r 3 modulator used in the isl6269a makes the lc output filter resemble a first order system in which the closed loop stability can be achieved with a type ii compensation network. your local intersil representative can provide a pc-based tool that can be used to ca lculate compensation network component values and help simulate the loop frequency response. the compensation network consists of the internal error amplifier of the isl6269a and the external components r1, r2, c1, and c2 as well as the frequency setting components r fset , and c fset, are identified in the schematic figure 6. general application design guide this design guide is intended to provide a high-level explanation of the steps neces sary to create a single-phase power converter. it is assumed th at the reader is familiar with many of the basic skills and te chniques referenced below. in v ref v out r bottom r top r bottom + --------------------------------------------------- ? = (eq. 5) r bottom v ref r ? top v out v ref ? ------------------------------------- = (eq. 6) f sw 1 kr fset ? --------------------------- = (eq. 7) r fset 1 kf sw ? ----------------- - = (eq. 8) gnd phase ug lg c out l out isl6269a q high_side r fset c fset q low_side ea + vin vin vo fb r2 r1 c1 c2 - fset comp ref c esr gate drivers dcr r 3 modulator vout figure 6. compensation reference circuit isl6269a
11 fn9253.2 may 30, 2007 addition to this guide, intersil provides complete reference designs that include schematics, bills of materials, and example board layouts. selecting the lc output filter the duty cycle of an ideal buck co nverter is a function of the input and the output voltage. this relationship is written as: the output inductor peak-to-peak ripple current is written as: a typical step-down dc/dc converter will have an i pp of 20% to 40% of the maximum dc output load current. the value of i pp is selected based upon se veral criteria such as mosfet switching loss, inductor core loss, and the resistive loss of the inductor winding. the dc copper loss of the inductor can be estimated by: where i load is the converter output dc current. the copper loss can be significant so attention has to be given to the dcr selection. another factor to consider when choosing the inductor is its saturation characteristics at elevated temperature. a saturated inductor could cause destruction of circuit components, as well as nuisance ocp faults. a dc/dc buck regulator must have output capacitance c out into which ripple current i pp can flow. current i pp develops a corresponding ripple voltage v pp across c out, which is the sum of the voltage drop across the capacitor esr and of the voltage change stemming from charge moved in and out of the capacitor. these two voltages are written as: and if the output of the converter has to support a load with high pulsating current, several capacitors will need to be paralleled to reduce the total esr until the required v pp is achieved. the inductance of the capacitor can cause a brief voltage dip if the load transient has an extremely high slew rate. low inductance capacitors constructed with reverse package geometry are available. a capacitor dissipates heat as a function of rms current and frequency. be sure that i pp is shared by a sufficient quantity of paralleled capacitors so that they operate below the maximum rated rms current at f sw . take into account that the rated value of a capacitor can fade as much as 50% as the dc voltage across it increases. selection of the input capacitor the important parameters for the bulk input capacitance are the voltage rating and the rms current rating. for reliable operation, select bulk capacitors with voltage and current ratings above the maximum input voltage and capable of supplying the rms current required by the switching circuit. their voltage rating should be at least 1.25 times greater than the maximum input voltage, while a voltage rating of 1.5 times is a preferred rating. figure 7 is a graph of the input rms ripple current, normalized relative to output load current, as a function of duty cycle t hat is adjusted for converter efficiency. the ripple current calculation is written as: where: -i max is the maximum continuous i load of the converter - x is a multiplier (0 to 1) corresponding to the inductor peak-to-peak ripple amplitude expressed as a percentage of i max (0% to 100%) - d is the duty cycle that is ad justed to take into account the efficiency of the conv erter which is written as: in addition to the bulk capacitance, some low esl ceramic capacitance is recommended to decouple between the drain of the high-side mosfet and t he source of the low-side mosfet. mosfet selection and considerations typically, a mosfet cannot tolerate even brief excursions beyond their maximum drain to source voltage rating. the mosfets used in the power stage of the converter should have a maximum v ds rating that exceeds the sum of the upper voltage tolerance of the input power source and the voltage spike that occurs when the mosfet switches off. there are several power mosfets readily available that are optimized for dc/dc converter applications. the preferred d v out v in --------------- - = (eq. 9) (eq. 10) i pp v out 1d ? () ? f sw l out ? ------------------------------------- - = (eq. 11) p copper i load 2 dcr ? = v esr i pp e ? sr = (eq. 12) ? sw ? ------------------------------------- = (eq. 13) (eq. 14) i in_rms i max 2 dd 2 ? () ? () xi max 2 d 12 ------ ?? ?? ?? + i max ---------------------------------------------------------------------------------------------------- - = d v out v in eff ? -------------------------- = (eq. 15) figure 7. normalized rms input current for x = 0.8 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 duty cycle normalized input rms ripple current x = 1 x = 0.75 x = 0.50 x = 0.25 x = 0 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 isl6269a
12 fn9253.2 may 30, 2007 high-side mosfet emphasizes low switch charge so that the device spends the least amount of time dissipating power in the linear region. unlike the low-side mosfet which has the drain-source voltage clamped by its body diode during turn off, the high-side mosfet turns off with v in -v out -v l across it. the preferred low-side mosfet emphasizes low r ds(on) when fully saturated to minimize conduction loss. for the low-side mosfet, (ls), the power loss can be assumed to be conductive only and is written as: for the high-side mosfet, (hs), its conduction loss is written as: for the high-side mosfet, its sw itching loss is written as: where: -i valley is the difference of the dc component of the inductor current minus 1/2 of the inductor ripple current -i peak is the sum of the dc component of the inductor current plus 1/2 of the inductor ripple current -t on is the time required to drive the device into saturation -t off is the time required to drive the device into cut-off selecting the bootstrap capacitor the selection of the bootstrap capacitor is written as: where: -q g is the total gate charge required to turn on the high-side mosfet - v boot , is the maximum allowed voltage decay across the boot capacitor each time the high-side mosfet is switched on as an example, suppose the high-side mosfet has a total gate charge q g , of 25nc at v gs = 5v, and a v boot of 200mv. the calculated bootstrap capacitance is 0.125f; for a comfortable margin select a capacitor that is double the calculated capacitance, in this example 0.22f will suffice. use an x7r or x5r ceramic capacitor. layout considerations as a general rule, power should be on the bottom layer of the pcb and weak analog or logic signals are on the top layer of the pcb. the ground-pl ane layer should be adjacent to the top layer to provide shielding. the ground plane layer should have an island located under the ic, the compensation components, and the fset components. the island should be connected to the rest of the ground plane layer at one point. signal ground and power ground the bottom of the isl6269a qfn package is the signal ground (gnd) terminal for analog and logic signals of the ic. connect the gnd pad of the isl6269a to the island of ground plane under the top layer using several vias, for a robust thermal and electrical conduction path. connect the input capacitors, the output capa citors, and the source of the lower mosfets to the power ground plane. pgnd (pin 10) this is the return path for the pull-down of the lg low-side mosfet gate driver. ideally, pgnd should be connected to the source of the low-side mosfet with a low-resistance, low-inductance path . vin (pin 1) the vin pin should be connected close to the drain of the high-side mosfet, using a low resistance and low inductance path. vcc (pin 2) for best performance, place the decoupling capacitor very close to the vcc and gnd pins. pvcc (pin 12) for best performance, place the decoupling capacitor very close to the pvcc and pgnd pins, preferably on the same side of the pcb as the isl6269a ic. fccm (pin 3), en (pin 4), and pgood (pin 16) these are logic inputs that are referenced to the gnd pin. treat as a typical logic signal. comp (pin 5), fb (pin 6), and vo (pin 8) for best results, use an isolat ed sense line from the output load to the vo pin. the input impedance of the fb pin is high, so place the voltage programming and loop compensation components close to the vo, fb, and gnd pins keeping the high impedance trace short. fset (pin 7) this pin requires a quiet environment. the resistor r fset and capacitor c fset should be placed directly adjacent to this pin. keep fast moving nodes away from this pin. (eq. 16) p con_ls i load 2 r ? ds on () _ls 1d ? () ? (eq. 17) p con_hs i load 2 r ? ds on () _hs d ? = (eq. 18) p sw_hs v in i valley t on f ? sw ? ? 2 ---------------------------------------------------------------- - v in i peak t off f ? sw ? ? 2 ------------------------------------------------------------- + = c boot q g v boot ----------------------- - = (eq. 19) inductor vias to ground plane vin vout phase node gnd output capacitors low-side mosfets input capacitors schottky diode high-side mosfets figure 8. typical power component placement isl6269a
13 fn9253.2 may 30, 2007 isen (pin 9) route the connection to the isen pin away from the traces and components connected to t he fb pin, comp pin, and fset pin. lg (pin 11) the signal going through this trace is both high dv/dt and high di/dt, with high peak charging and discharging current. route this trace in parallel with the trace from the pgnd pin. these two traces should be short, wide, and away from other traces. there should be no other weak signal traces in proximity with these traces on any layer. boot (pin 13), ug (pin 14), and phase (pin 15) the signals going through thes e traces are both high dv/dt and high di/dt, with high peak charging and discharging current. route the ug and phase pi ns in parallel with short and wide traces. there should be no other weak signal traces in proximity with these traces on any layer. copper size for the phase node the parasitic capacitance and parasitic inductance of the phase node should be kept very low to minimize ringing. it is best to limit the size of the phase node copper in strict accordance with the current and thermal management of the application. an mlcc should be connected directly across the drain of the upper mosfet and the source of the lower mosfet to suppress the turn-off voltage spike. isl6269a
14 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn9253.2 may 30, 2007 isl6269a quad flat no-lead plastic package (qfn) micro lead frame pl astic package (mlfp) l16.4x4 16 lead quad flat no-lead plastic package (compliant to jedec mo-220-vggc issue c) symbol millimeters notes min nominal max a 0.80 0.90 1.00 - a1 - - 0.05 - a2 - - 1.00 9 a3 0.20 ref 9 b 0.23 0.28 0.35 5, 8 d 4.00 bsc - d1 3.75 bsc 9 d2 1.95 2.10 2.25 7, 8 e 4.00 bsc - e1 3.75 bsc 9 e2 1.95 2.10 2.25 7, 8 e 0.65 bsc - k0.25 - - - l 0.50 0.60 0.75 8 l1 - - 0.15 10 n162 nd 4 3 ne 4 3 p- -0.609 --129 rev. 5 5/04 notes: 1. dimensioning and tolerances conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd and ne refer to the number of terminals on each d and e. 4. all dimensions are in millimeters. angles are in degrees. 5. dimension b applies to the meta llized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are fo r the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are provided to assist with pcb land pattern design efforts, see intersil technical brief tb389. 9. features and dimensions a2, a3, d1, e1, p & are present when anvil singulation method is used and not present for saw singulation. 10. depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (l1) maybe present. l minus l1 to be equal to or greater than 0.3mm.

▲Up To Search▲

Price & Availability of ISL6269ACRZ

	To Download ISL6269ACRZ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .